1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method, a semiconductor device, and a wafer. More particularly, to a three-dimensional semiconductor device formed by laminating a plurality of semiconductor devices, a method of manufacturing such a three-dimensional semiconductor device and a wafer.
2. Description of the Related Art
Conventionally, a three-dimensional semiconductor integrated circuit device has been known having a structure in which two or more wafers are vertically laminated and are electrically connected therebetween with buried interconnect. For example, Japanese Patent Laid-Open Publication No. H11-261000 (hereinafter referred to as a patent document) discloses a method of manufacturing a three-dimensional semiconductor integrated circuit device. In this method, firstly, a trench (deep trench) is formed on one of wafers to be laminated. Then, after the inside of the trench is thermally oxidized, polysilicon is buried in that trench as a conductor to form buried interconnect. Then, the wafer is made thinner until the buried interconnect is exposed, and an undersurface bump is formed at the position of each of the buried interconnect on the undersurface of the wafer. Then, after laminating the undersurface bumps of the wafer and the top-surface bumps formed on the top surface of the other one of the wafers to be laminated, an insulating adhesive is injected between these two laminated wafers to manufacture a three-dimensional semiconductor integrated circuit device. According to this manufacturing method, undersurface bumps for connection have to be formed on the undersurface of one of two wafers to be laminated, and top-surface bumps for connection have to be formed on the top surface of the other wafer. After these bumps are connected together, an adhesive is injected between the two laminated wafers and hardened, thereby manufacturing a three-dimensional semiconductor integrated circuit device. Further lamination of layers can be achieved by repeating these processes described above.
Here, a process flow of laminating two wafers, upper and lower, is schematically shown in FIG. 1. For formation of an upper wafer, after the wafer is installed, isolation is performed through a normal process to form an element, such as a transistor. Before or after transistor formation, the above-described buried interconnect is formed. In that case, when an insulating film and the buried interconnect are formed at a high buried-interconnect forming temperature, which will affect transistor characteristics (for example, when a deep hole is formed through etching and, after the surface is oxidized, polysilicon is buried as the buried interconnect), a buried interconnect is formed before transistor formation. On the other hand, when the buried-interconnect forming temperature does not affect the transistor characteristics (for example, when a deep hole is formed through etching and, after an insulating film is deposited, a metal interconnect is buried), a buried interconnect is formed after transistor formation. Then, the following processes are sequentially performed: a multilayer interconnect process of connecting the elements, wafer thinning process, a process of forming an undersurface insulating film to prevent a short circuit between the buried interconnect or undersurface bumps later formed and a substrate (silicon), and a process of forming undersurface bumps for connecting buried interconnect of the upper wafer and the lower wafer.
Next, the other one (lower wafer) of the wafers to be laminated is formed by performing processes similar to those for the upper wafer described above until the multilayer interconnect process. That is, the processes are approximately similar to those for the upper wafer except the process of making the wafer thinner, the process of forming an undersurface insulating film, and the process of forming undersurface bumps. However, for the last wafer formed to be laminated, the process of forming a buried interconnect may be omitted. On the top surface of the lower wafer, bumps are formed for connection to the buried interconnect of the upper wafer. Then, position alignment is performed between the upper and lower wafers (alignment between the laminated wafers), the upper and lower wafers are attached together and, furthermore, an adhesive is injected between the wafers to increase mechanical strength of the device.
Meanwhile, when the technology disclosed in the above patent document is used, after a buried interconnect is formed, the wafer is made thinner until the buried interconnect is exposed, and bumps are formed at the position of the buried interconnect on the undersurface of the wafer. When making the wafer thinner, for allowing wafer handling, a glass plate serving as a supporting substrate is bonded on the main surface of the wafer with a adhesive sheet or its alternative, and then the undersurface of the wafer is grinded or polished by using, for example, a grinding device using a grinding stone or a CMP (Chemical Mechanical Polishing) device using slurry for polishing, to make the wafer thinner. However, at the time of grinding the wafer, buried interconnect material or silicon ground by the grinding stone may cause the grinding stone to be clogged. Also, with a long grinding time, the temperature of the grinding stone is increased to cause the wafer to be burnt and cracked. As such, a problem arises in which the wafer to be made thinner is damaged. In recent years, the diameter of the wafer has been increased in view of, for example, increasing the number of chips obtainable from one wafer to enhance manufacturing yields. However, as the diameter of the wafer is increased, it has to take a sufficient amount of time to grind or polish the wafer accordingly. Moreover, in view of ensuring mechanical strength of the wafer, for example, the thickness of the wafer in manufacturing the wafer has to be thicker to some extent. This also increases the time to grind or polish the wafer. Therefore, the problem as described above becomes more significant.
Furthermore, in the technology disclosed in the above patent document, at the time of forming bumps on the undersurface of the wafer to be laminated, in order to insulate the substrate from the bumps, an insulating film is formed on the undersurface of the wafer through, for example, CVD (Chemical Vapor Deposition) or sputtering, after the wafer is made thinner. In this case, however, the processing temperature at the time of forming an insulating film on the undersurface of the wafer is important. That is, in this process, there is a problem in which the thin wafer may be cracked due to the buried interconnect material in the wafer or a film stress of the insulating film attached to the undersurface. Moreover, the insulating film is formed on the undersurface of the wafer in a state where, in view of keeping mechanical strength of the thin wafer, the glass supporting substrate used at the time of wafer thinning is kept attached to the main surface of the wafer. However, the temperature for attaching the insulating film formed on the undersurface of the wafer is higher than the allowable temperature limit of the adhesive sheet for bonding the wafer and the glass substrate. For this reason, a problem arises in which, in the process of forming an insulating film on the undersurface of the wafer, the bonding force of the adhesive sheet is decreased to cause the glass supporting substrate to fall off.
Still further, in the technology disclosed in the above patent document, contact holes have to be formed at positions where bumps are formed on the undersurface of the wafer for connecting the buried interconnects and the bumps. These contact holes are small, and alignment of a photomask for forming these holes is difficult. Moreover, to form bumps on the undersurface of the wafer, cumbersome processes are required, including a series of lithography processing, such as application of a resist, exposure, and development, and etching with a resist pattern formed through the lithography processing as a mask. This poses another problem of increasing the manufacturing time.